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ST72F324J2TA Datasheet(PDF) 142 Page - STMicroelectronics |
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ST72F324J2TA Datasheet(HTML) 142 Page - STMicroelectronics |
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142 / 167 page  ST72324B 142/167 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 78. SPI Slave Timing Diagram with CPHA=11) Figure 79. SPI Master Timing Diagram 1) Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. SS INPUT CPHA=1 MOSI INPUT MISO OUTPUT CPHA=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN SS INPUT CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 CPHA=1 CPHA=1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) tv(MO) th(MO) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN seenote2 seenote2 CPOL=0 CPOL=1 CPOL=0 CPOL=1 tr(SCK) tf(SCK) 1 |
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