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I.MX8XLITE Datasheet(PDF) 20 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 112 page ![]() Table 8. i.MX 8XLite Key State (KSx) power consumption (continued) Mode Test conditions Supply Max Unit KS1 1 SCU RAMs and IO state retained. DRAM in self-refresh, associated I/O’s OFF. 32K running, 24M, PLLs and ring oscillators OFF. PHYs are in idle state. MEMC supplies OFF. DDR_PLL ON MAIN 3 dropped to 0.8 V. VDD_ANAx_1P8 (1.8 V) 0.9 mA VDD_MEMC (OFF) - mA VDD_MAIN (0.8 V) 6.4 mA VDD_DDR_VDDQ 4 (1.1 V) 1 mA Total 7.84 mW KS4 5 Leakage test, not intended as a customer use case. Overdrive conditions set, memories active, all sub-systems powered ON. Active power minimized. VDD_ANAx_1P8 (1.8 V) 11 mA VDD_MEMC (1.1 V) 1313 mA VDD_MAIN (1.0 V) 405 mA Total 1869 mW 1. Maximum values are for 25 °C Tambient. 2. Maximum values are for 125 °C Tjunction. 3. 0.8 V nominal—voltage specification under this case is ±3%. 4. VDD_DDR_VDDQ may be turned off during self refresh if compliant with the JEDEC specification for the DRAM device and power supply design. 5. Maximum values are for 125 °C Tjunction. Stated supply voltage do not exceed +2% during test. 3.1.7 USB 2.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 9. USB 2.0 PHY typical current consumption in Power-Down Mode VDD_USB_3P3 (3.3 V) VDD_USB_1P8 (1.8 V) Current 180 μA 60 μA 3.2 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase Electrical characteristics 20 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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