I.MX8XLITE datasheet(27/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

PDF	112 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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3.3.2 PLLs dedicated to specific interfaces

The following sections cover PLLs used for specific interfaces. Clock output

frequency and clock output range refer to the output of the PLL. Additional clock

dividers may be on the output path to divide the output frequency down to the targeted

frequency. See the related sections in the reference manual for settings of these clock

dividers.

3.3.2.1 Audio PLL

This PLL is controlled by the SCU.

Table 12. Audio PLL

Parameter

Value

Unit

Reference clock

24

MHz

3.3.2.2 USB 2.0 B PLLs

USB 2.0 B has one PLL . It is embedded in the USB 2.0 OTG PHY B .

The table below describes the PLL embedded in the USBOTG PHY.

Table 13. USB 2.0 PLL embedded in USBOTG PHY

Parameter

Value

Unit

Reference clock

24

MHz

Clock output frequency

480

MHz

3.3.2.3 PCIe PLLs

The PCIe interface has three PLLs:

• One is used to generate the single, common 100 MHz reference clock to each lane

• One Transmit and one Receive PLL in one lane

The table below shows the characteristics for the reference clock PLL.

Electrical characteristics

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

27

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