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I.MX8XLITE Datasheet(PDF) 56 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 112 page  Table 43. Toggle mode timing parameters 1 (continued) ID Parameter Symbol Timing T = GPMI Clock Cycle Uni t Min. Max. NF18 NAND_CEx_B access time tCE CE_DELAY × T [see notes 2, 4] — ns NF22 clock period tCK — — ns NF23 preamble delay tPRE PRE_DELAY × T [see notes 2, 5] — ns NF24 postamble delay tPOST POST_DELAY × T +0.43 [see note 2 ] — ns NF28 Data write setup tDS 6 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH 6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 7 — 3.18 NF31 NAND_DQS/NAND_DQ read hold skew tQHS 7 — 3.27 1. The GPMI toggle mode output timing can be controlled by the module’s internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2. AS minimum value can be 0, while DS/DH minimum value is 1. 3. T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 4. CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level. 5. PRE_DELAY+1) ≥ (AS+DS) 6. Shown in "Toggle mode data write timing". 7. Shown in "Toggle mode data read timing". For DDR Toggle mode, Figure 22 shows the timing diagram of NAND_DQS/ NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 3.10 External Peripheral Interface Parameters The following subsections provide information on external peripheral interfaces. Electrical characteristics 56 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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