I.MX8XLITE datasheet(58/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

PDF	112 Pages

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Manufacturer	NXP [NXP Semiconductors]

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Table 45. LPSPI timings—Master mode at 60 MHz

ID

Parameter

Min

Max

Unit

— SPIx_SCLK Cycle frequency

—

60

MHz

t1

SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

7.5

—

ns

t2

SPIx_CSy pulse width

7.5

—

ns

t3

SPIx_CSy Lead Time(1)

FCLK_PERIOD(2) x (PCSSCK + 1) /

2PRESCALE - 3

—

ns

t4

SPIx_CSy Lag Time(3)

FCLK_PERIOD(2) x (SCKPCS + 1) /

2PRESCALE + 3

—

ns

t5

SPIx_SDO output Delay (CLOAD = 20 pF)

—

3

ns

t6

SPIx_SDI Setup Time

2

—

ns

t7

SPIx_SDI Hold Time

2

—

ns

1. This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

2. FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

3. This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

Table 46. LPSPI timings—Master mode at 40 MHz

ID

Parameter

Min

Max

Unit

— SPIx_SCLK Cycle frequency

—

40

MHz

t1

SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

11

—

ns

t2

SPIx_CSy pulse width

11

—

ns

t3

SPIx_CSy Lead Time(1)

FCLK_PERIOD(2) x (PCSSCK + 1) /

2PRESCALE + 3

—

ns

t4

SPIx_CSy Lag Time(3)

FCLK_PERIOD(2) x (SCKPCS + 1) /

2PRESCALE + 3

—

ns

t5

SPIx_SDO output Delay (CLOAD = 20 pF)

—

5

ns

t6

SPIx_SDI Setup Time

5

—

ns

t7

SPIx_SDI Hold Time

4

—

ns

1. This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

2. FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

3. This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

Electrical characteristics

58

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

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