I.MX8XLITE datasheet(60/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

PDF	112 Pages

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Manufacturer	NXP [NXP Semiconductors]

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3.10.2 Serial audio interface (SAI) timing parameters

The timings and figures in this section are valid for noninverted clock polarity

(I2S_TCR2.BCP = 0b0, I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity

(I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP = 0b0). If the polarity of the clock and/or the

frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown in the

figures below.

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated.

Note

SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3

are receive only.

3.10.2.1 SAI Master Synchronous mode

In this mode, transmitter clock and frame sync are used by both transmitter and receiver

(I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires

only 4 signals to be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD.

SAI_RXC and SAI_RXFS can be left unconnected. I2S_RCR2.BCI shall be set to 0b1

to get setup and hold times provided in Table 49.

Figure 25. SAI Master Synchronous mode

Electrical characteristics

60

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

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