I.MX8XLITE datasheet(67/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

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Manufacturer	NXP [NXP Semiconductors]

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Output from uSDHC to card

Input from card to uSDHC

SCK

SD4

SD5

SD7

SD6

SD2

SD1

SD3

SD8

Figure 32. SDR50/SDR104 timing

Table 56. SDR50/SDR104 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

4.8

—

ns

SD2

Clock Low Time

tCL

0.46 × tCLK

0.54 × tCLK

ns

SD3

Clock High Time

tCH

0.46 × tCLK

0.54 × tCLK

ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD4

uSDHC Output Delay

tOD

–3

1

ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)

SD5

uSDHC Output Delay

tOD

–1.6

1

ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD6

uSDHC Input Setup Time

tISU

2.5

—

ns

SD7

uSDHC Input Hold Time

tIH

1.5

—

ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)1

SD8

Card Output Data Window

tODW

0.5 × tCLK

—

ns

1. Data window in SDR100 mode is variable.

3.10.3.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling

Both SD and EMMC standards utilize 3.3 and 1.8V signaling levels, depending on the

card type. Higher bus frequencies like SDR50/SDR104 for SD and HS200/HS400 for

EMMC require 1.8V signaling. The DC parameters for the

VDD_USDHC1_VSELECT_1P8_3P3, VDD_ENET0_1P8_3P3,

VDD_ENET0_VSELECT_1P8_3P3 supplies that power the USDHC I/O are identical

to those shown in Table 20 and Table 21.

Electrical characteristics

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

67

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