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I.MX8XLITE Datasheet(PDF) 70 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 70 Page - NXP Semiconductors |
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70 / 112 page ![]() Figure 34. RGMII timing diagram—Internal-Delay mode Table 59. RGMII timing—Internal-Delay mode ID Parameter Min Typ Max Unit TXC / RXC frequency — 125 — MHz t1 Clock cycle 7.2 8 8.8 ns t2 TXD setup time 1.2 — — ns t3 TXD hold time 1.2 — — ns t4 RXD setup time 0 — — ns t5 RXD hold time 2.5 — — ns 3.10.4.2 RMII RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated internally and provided to the PHY through RCLK50M_OUT. Or, it come from and external 50MHz clock generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin. Electrical characteristics 70 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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