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I.MX8XLITE Datasheet(PDF) 74 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 112 page  Table 63. I2C timing Fast Mode Plus High Speed1 Unit ID Parameter Min Max Min Max IC1 SCL clock frequency — 1 — 3.4 MHz IC2 Hold time (repeated) START condition 260 — 160 — ns IC3 Set-up time for STOP condition 260 — 160 — ns IC4 Data hold time 0 — 0 70 ns IC5 HIGH Period of I2Cx_SCL Clock 260 — 60 — ns IC6 LOW Period of the I2Cx_SCL Clock 500 — 160 — ns IC7 Set-up time for a repeated START condition 260 — 160 — ns IC8 Data set-up time 50 — 10 — ns IC9 Bus free time between a STOP and START condition 500 — 150 — ns IC10 Rise time of I2Cx_SDA signals — 120 10 80 ns IC11 Fall time of I2Cx_SDA signals 12 (@3.3 V) 6.5 (@1.8 V) 120 10 80 ns IC10b Rise time of I2Cx_SCL signals — 120 10 40 ns IC11b Fall time of I2Cx_SCL signals 12 (@3.3 V) 6.5 (@1.8 V) 120 10 40 ns IC12 Capacitive load for each bus line (Cb) — 550 — 100 pF 1. High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems. 3.10.7 PCIe 3.0 PHY Parameters Please refer to the PCIe standard specifications. The PHY is compliant with the PCIe 3.0 specification. 3.10.7.1 PCIE_REXT reference resistor connection PCIE_REXT is the reference resistor for the impedance of the internal termination resistors on the signal lines. Internal termination must match the differential impedance of the PCB routing. The following figure shows the PCIE_REXT reference resistor connection. Electrical characteristics 74 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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