I.MX8XLITE datasheet(76/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

PDF	112 Pages

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Manufacturer	NXP [NXP Semiconductors]

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Table 64. PWM Output Timing Parameters

ID

Parameter

Min

Max

Unit

—

PWM Module Clock Frequency

0

ipg_clk

MHz

P1

PWM output pulse width high

15

—

ns

P2

PWM output pulse width low

15

—

ns

3.10.9 LCD controller (LCDIF) parameters

Figure 40 shows the LCDIF timing, and the table below lists the timing parameters.

L1

L2

L3

L4

LCDn_CLK

(falling edge capture)

LCDn_CLK

(rising edge capture)

LCDn_DATA[23:00]

LCDn Control Signals

L5

L6

L7

Figure 40. LCD Timing

Table 65. LCD Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

L1

LCD pixel clock frequency

tCLK(LCD)

—

80

MHz

L2

LCD pixel clock high (falling edge capture)

tCLKH(LCD)

6

—

ns

L3

LCD pixel clock low (rising edge capture)

tCLKL(LCD)

6

—

ns

L4

LCD pixel clock high to data valid (falling edge capture)

td(CLKH-DV)

-1

1

ns

L5

LCD pixel clock low to data valid (rising edge capture)

td(CLKL-DV)

-1

1

ns

L6

LCD pixel clock high to control signal valid (falling edge capture)

td(CLKH-

CTRLV)

-1

1

ns

L7

LCD pixel clock low to control signal valid (rising edge capture)

td(CLKL-CTRLV)

-1

1

ns

3.10.9.1 LCDIF signal mapping

The table below lists the details about the mapping signals.

Electrical characteristics

76

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

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