I.MX8XLITE datasheet(81/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

PDF	112 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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Figure 45. FlexSPI read timing diagram (DDR mode)

QSPIx[A/B]_DQS

QSPIx[A/B]_DATAy

t9

t10

Figure 46. FlexSPI read with DQS timing diagram (DDR mode)

Table 70. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode)

ID

Parameter

Min

Max

Unit

— QSPIx[A/B]_SCLK Cycle frequency

—

30

MHz

t1

QSPIx[A/B]_SCLK High or Low Time

15

—

ns

t2

QSPIx[A/B]_SSy_B pulse width

1

—

SCLK

t3

QSPIx[A/B]_SSy_B Lead Time 1

(TCSS+0.5)/2

—

SCLK

t4

QSPIx[A/B]_SSy_B Lag Time 1

(TCSH+0.5)/2

—

SCLK

t5

QSPIx[A/B]_DATAy output valid time

6.5

—

ns

t6

QSPIx[A/B]_DATAy output hold time

6.5

—

ns

t7

QSPIx[A/B]_DATAy Setup Time

6

—

ns

t8

QSPIx[A/B]_DATAy Hold Time

0

—

ns

1. Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 71. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode)

ID

Parameter

Min

Max

Unit

— QSPIx[A/B]_SCLK Cycle frequency

—

83

MHz

t1

QSPIx[A/B]_SCLK High or Low Time

5.4

—

ns

t2

QSPIx[A/B]_SSy_B pulse width

1

—

SCLK

t3

QSPIx[A/B]_SSy_B Lead Time 1

(TCSS+0.5)/2

—

SCLK

t4

QSPIx[A/B]_SSy_B Lag Time 1

TCSH/2

—

SCLK

t5

QSPIx[A/B]_DATAy output valid time

2

—

ns

t6

QSPIx[A/B]_DATAy output hold time

2

—

ns

t7

QSPIx[A/B]_DATAy Setup Time

1

—

ns

t8

QSPIx[A/B]_DATAy Hold Time

1

—

ns

Electrical characteristics

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

81

NXP Semiconductors

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