I.MX8XLITE datasheet(82/112 Pages) NXP

Part #	I.MX8XLITE

Description	i.MX 8XLite Industrial Applications Processors

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Manufacturer	NXP [NXP Semiconductors]

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1. Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 72. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode)

ID

Parameter

Min

Max

Unit

— QSPIx[A/B]_SCLK Cycle frequency

—

200

MHz

t1

QSPIx[A/B]_SCLK High or Low Time

2.25

—

ns

t2

QSPIx[A/B]_SSy_B pulse width

1

—

SCLK

t3

QSPIx[A/B]_SSy_B Lead Time 1

(TCSS+0.5)/2

—

SCLK

t4

QSPIx[A/B]_SSy_B Lag Time 1

TCSH/2

—

SCLK

t5

QSPIx[A/B]_DATAy output valid time

0.65

—

ns

t6

QSPIx[A/B]_DATAy output hold time

0.65

—

ns

t9

QSPIx[A/B]_DATAy Setup Skew

—

0.65

ns

t10 QSPIx[A/B]_DATAy Hold Skew

—

0.65

ns

1. Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

3.10.11 Secure JTAG controller (SJC)

3.10.11.1 Internal pull-up/pull-down configuration

The following table describes the default configuration of internal pull-ups and pull-

downs of the JTAG interface. External pull-ups and pull-downs are needed when this

interface is routed to a connector.

Table 73. JTAG default configuration for internal pull-up/pull-down

Ball name

Internal pull setting1

Typical pull

value

Unit

JTAG_TMS

PU

50

KΩ

JTAG_TCK

PD

JTAG_TDI

PU

TEST_MODE_SELECT

PD

1. PU = pull-up; PD = pull-down

3.10.11.2 JTAG timing parameters

Figure 47 depicts the SJC test clock input timing. Figure 48 depicts the SJC boundary

scan timing. Figure 49 depicts the SJC test access port. Signal parameters are listed in

Table 74.

Electrical characteristics

82

i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023

NXP Semiconductors

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