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I.MX8XLITE Datasheet(PDF) 87 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 87 Page - NXP Semiconductors |
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87 / 112 page  Table 78. IrDA Mode Transmit Timing Parameters ID Parameter Symbol Min Max Uni t UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate1 – Tref_clk2 1/Fbaud_rate + Tref_clk — UA4 Transmit IR Pulse Duration tTIRpulse (TNP+1)/(OSR+1) × (1/ Fbaud_rate) – Tref_clk (TNP+1)/(OSR+1) × (1/ Fbaud_rate) + Tref_clk — 1. Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/ (SBR[12:0] × (OSR+1)). 2. Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). 3.10.13.3.2 UART IrDA Mode Receiver The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 79 lists the receive timing characteristics. Bit 1 Bit 2 Bit 0 Bit 4 Bit 5 Bit 6 Bit 7 Bit 3 STOP BIT POSSIBLE PARITY BIT UA5 UA5 UA5 UA5 UA6 Start Bit UARTx_RX_DATA (input) Figure 55. UART IrDA Mode Receive Timing Diagram Table 79. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min Max Unit UA5 Receive Bit Time 1 in IrDA mode tRIRbit 1/Fbaud_rate2 – 1/(16 × Fbaud_rate) 1/Fbaud_rate + 1/(16 × Fbaud_rate) — UA6 Receive IR Pulse Duration tRIRpulse 1.41 μs (5/16) × (1/Fbaud_rate) — 1. The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/((OSR+1) × Fbaud_rate). 2. Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/ (SBR[12:0] × (OSR+1)). 3.10.14 USB 2.0 PHY Parameters The USB2 OTG module has been specified to perform USB 2.0 dual role and USB 2.0 On-The-Go(OTG) compatible with the USB 2.0 specification and with OTG supplementary specifications. 3.10.14.1 USB 2.0 PHY ID-pin specifications The following table lists the ID-pin specifications for USB2.0 PHY. Electrical characteristics i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 87 NXP Semiconductors |
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