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I.MX8XLITE Datasheet(PDF) 90 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 90 Page - NXP Semiconductors |
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90 / 112 page  Table 83. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8) (continued) Symbol Description Min Typ1 Max Unit Notes Avg = 2 9.9 10.1 — Bits Avg = 16 10.8 11 — Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB — EG Gain error — 0.29 — %FSV 8 EO Offset error — 0.01 — %FSV 9 IVDDA18 Supply Current — 480 — μA 10 Iin,ext,leak External Channel Leakage Current — 30 500 nA — EIL Input leakage error RAS * Iin mV — 1. Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2. This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3. See "Sample time vs. RAS". 4. ADC conversion clock at max frequency and using linear histogram. 5. Input data used for test was 1 kHz sine wave. 6. Measured at VREFH = 1 V and pwrsel = 2. 7. ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8. Error measured at fullscale at 1.0 V. 9. Error measured at zero scale at 0 V. 10. Power Configuration Select, PWRSEL, is set to 10 binary. The following figure shows a plot of the ADC sample time versus RAS. Electrical characteristics 90 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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