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I.MX8XLITE Datasheet(PDF) 97 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 97 Page - NXP Semiconductors |
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97 / 112 page  NXP Semiconductors 97 i. MX 8XLite Industrial Applications Processors, Rev.3 08/2023 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A VSS_MAIN DDR_DCF22 DDR_DCF09 DDR_DCF04 PCIE_CTRL0_ WAKE_B PCIE0_TX0_P PCIE0_RX0_P PCIE_REFCL K100M_P USB_OTG2_D P USB_OTG1_D N EMMC0_DAT A7 EMMC0_DAT A0 EMMC0_DAT A5 EMMC0_CMD USDHC1_RES ET_B ENET0_RGMII _RXD3 ENET0_RGMII _RXD1 VSS_MAIN B DDR_DCF20 DDR_DCF17 DDR_DCF19 PCIE_CTRL0_ PERST_B PCIE0_TX0_N PCIE0_RX0_N PCIE_REFCL K100M_N USB_OTG2_D N USB_OTG1_D P EMMC0_DAT A6 EMMC0_DAT A1 EMMC0_DAT A3 EMMC0_RES ET_B USDHC1_VSE LECT USDHC1_WP ENET0_RGMII _RXD0 ENET0_RGMII _RXC C VSS_MAIN VSS_MAIN DDR_DCF32 VSS_MAIN PCIE_CTRL0_ CLKREQ_B VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN USB_OTG1_ID EMMC0_DAT A2 EMMC0_DAT A4 EMMC0_STR OBE EMMC0_CLK USDHC1_CD_ B ENET0_RGMII _RXD2 ENET0_RGMII _RX_CTL ENET0_RGMII _TX_CTL D VSS_MAIN ENET0_REFC LK_125M_25M E DDR_DCF24 DDR_DCF27 VSS_MAIN VSS_MAIN VSS_MAIN VDD_PCIE_L DO_1P0_CAP VSS_MAIN VDD_ANA0_1 P8 VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN ENET0_MDC ENET0_MDIO F DDR_DCF23 ENET1_RGMII _RXD1 G DDR_DCF26 VSS_MAIN VSS_MAIN N.C. PCIE_REXT PCIE_REF_Q R USB_OTG2_V BUS USB_OTG2_ID USB_OTG1_V BUS USB_SS3_TC 1 USB_SS3_TC 0 USB_SS3_TC 3 USB_SS3_TC 2 ENET0_RGMII _TXC ENET0_RGMII _TXD1 VSS_MAIN ENET1_RGMII _RXC ENET1_RGMII _RXD3 H DDR_DCF18 ENET1_RGMII _RXD2 J DDR_DCF01 DDR_DCF03 VSS_MAIN DDR_DCF28 DDR_DCF33 PCIE0_PHY_P LL_REF_RET URN VDD_PCIE_1 P8 N.C. VDD_USB_SS 3_LDO_1P0_ CAP VDD_USB_1P 8 VDD_USB_3P 3 VDD_EMMC0 _1P8_3P3 VDD_EMMC0 _1P8_3P3 VDD_USDHC 1_VSELECT_ 1P8_3P3 ENET0_RGMII _TXD0 VSS_MAIN ENET1_RGMII _RXD0 ENET1_RGMII _RX_CTL K DDR_CK0_N ENET1_REFC LK_125M_25M L DDR_CK0_P VSS_MAIN VSS_MAIN DDR_DCF30 VDD_PCIE_DI G_1P8_3P3 VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_ENET0_ VSELECT_1P 8_3P3 ENET0_RGMII _TXD2 VSS_MAIN ENET1_RGMII _TXD3 ENET1_RGMII _TXC M DDR_DCF05 ENET1_RGMII _TXD2 N DDR_DCF00 DDR_DCF08 VSS_MAIN VDD_DDR_V DDQ VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN VSS_MAIN VDD_ENET0_ 1P8_3P3 ENET0_RGMII _TXD3 VSS_MAIN ENET1_RGMII _TXD0 ENET1_RGMII _TXD1 P DDR_DCF15 SPI3_SCK R DDR_DCF10 VSS_MAIN VSS_MAIN VDD_DDR_V DDQ VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VDD_MAIN VDD_MAIN VSS_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_ENET_M DIO_1P8_3P3 ENET1_RGMII _TX_CTL VSS_MAIN SPI3_SDI SPI3_SDO T DDR_DCF14 SPI3_CS0 U DDR_DCF16 DDR_DCF12 VSS_MAIN VDD_DDR_V DDQ VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VSS_MAIN VSS_MAIN VDD_MEMC VSS_MAIN VDD_MAIN VSS_MAIN VDD_ESAI_S PDIF_1P8_3P 3 SPI3_CS1 VSS_MAIN MCLK_IN0 MCLK_IN1 V DDR_DCF21 MCLK_OUT0 W DDR_DCF11 VSS_MAIN VSS_MAIN VDD_DDR_PL L_1P8 VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VDD_MEMC VDD_MEMC VDD_MEMC VSS_MAIN VDD_MAIN VSS_MAIN VDD_SPI_MC LK_UART_1P8 _3P3 UART1_RTS_ B VSS_MAIN UART1_RX UART1_TX Y DDR_DCF07 SPI0_SCK AA DDR_DQ14 DDR_DQ15 VSS_MAIN VDD_DDR_V DDQ VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_SPI_SAI _1P8_3P3 UART1_CTS_ B VSS_MAIN SPI0_SDI SPI0_SDO AB DDR_DQ13 SPI0_CS0 AC DDR_DQ12 VSS_MAIN VSS_MAIN DDR_ATO VDD_DDR_V DDQ VSS_MAIN VDD_MEMC VDD_MEMC VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN VSS_MAIN VDD_ADC_1P 8 ADC_VREFH VSS_MAIN ADC_IN2 SPI0_CS1 AD DDR_DQS1_N ADC_IN0 AE DDR_DM1 DDR_DQS1_P VSS_MAIN VDD_DDR_V DDQ VDD_DDR_V DDQ VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_ADC_DI G_1P8 ADC_VREFL VSS_MAIN ADC_IN4 ADC_IN1 AF DDR_DQ11 ADC_IN3 AG DDR_DQ10 VSS_MAIN VSS_MAIN DDR_DTO0 DDR_DTO1 VDD_QSPI0B _1P8_3P3 VDD_QSPI0A _1P8_3P3 VDD_CSI_1P8 _3P3 VDD_TMPR_C SI_1P8_3P3 VDD_SNVS_L DO_1P8_CAP VDD_SNVS_4 P2 RTC_XTALI XTALI VDD_CAN_UA RT_1P8_3P3 JTAG_TRST_B VSS_MAIN VSS_MAIN ADC_IN5 AH DDR_DQ09 FLEXCAN0_R X AJ DDR_DQ00 DDR_DQ08 VSS_MAIN DDR_ZQ DDR_VREF QSPI0B_SS0_ B SNVS_TAMPE R_IN4 SNVS_TAMPE R_IN3 SNVS_TAMPE R_IN2 ANA_TEST_O UT_P ANA_TEST_O UT_N RTC_XTALO XTALO VDD_ANA1_1 P8 SCU_BOOT_M ODE2 VSS_MAIN FLEXCAN1_R X FLEXCAN0_T X AK DDR_DQ01 FLEXCAN1_T X AL DDR_DQ02 VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN FLEXCAN2_T X FLEXCAN2_R X AM DDR_DQ03 UART0_RX AN DDR_DQS0_P DDR_DM0 VSS_MAIN QSPI0A_SS0_ B QSPI0A_DATA 2 QSPI0A_DATA 3 QSPI0A_DATA 1 QSPI0B_DQS SNVS_TAMPE R_IN1 SNVS_TAMPE R_IN0 SNVS_TAMPE R_OUT2 SNVS_TAMPE R_OUT4 SCU_PMIC_S TANDBY PMIC_INT_B TEST_MODE_ SELECT JTAG_TDO UART2_RX UART0_TX AP DDR_DQS0_N DDR_DQ05 DDR_DQ07 QSPI0A_SCLK QSPI0B_DATA 0 QSPI0B_DATA 1 QSPI0B_DATA 3 SPI1_SCK SPI1_SDI SNVS_TAMPE R_OUT3 SNVS_TAMPE R_OUT0 SNVS_TAMPE R_OUT1 SCU_GPIO0_0 1 PMIC_I2C_SD A PMIC_I2C_SC L JTAG_TMS UART2_TX AR VSS_MAIN DDR_DQ04 DDR_DQ06 QSPI0B_SCLK QSPI0A_DQS QSPI0A_DATA 0 QSPI0B_DATA 2 SPI1_CS0 SPI1_SDO PMIC_ON_RE Q ON_OFF_BUT TON SCU_BOOT_M ODE0 SCU_BOOT_M ODE1 SCU_GPIO0_0 0 POR_B JTAG_TDI JTAG_TCK VSS_MAIN Package information and functional assignments for FCPBGA, 15 x 15 mm, 0.56 and 0.8 mm mixed pitch |
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