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I.MX8XLITE Datasheet(PDF) 12 Page - NXP Semiconductors |
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I.MX8XLITE Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 112 page  Table 2. i.MX 8XLite modules list (continued) Block Mnemonic Block Name Brief Description • Hardware support for OTG signaling • Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software uSDHC SD/eMMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller The uSDHC is a host controller used to communicate with external low cost data storage and communication media. It supports the previous versions of the MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the uSDHC supports: • SD Host Controller Standard Specification v3.0 with the exception that all the registers do not match the standards address mapping. • SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50) • SDIO specification v3.0 • eMMC System Specification v5.1 • Three identical uSDHC controllers are available: one with 8-bit data to support eMMC, two with 4-bit data for SD/SDIO V2X Standalone Cryptographic Accelerator The V2X is a standalone cryptographic accelerator which is intended to allow processing of cryptographic operations from the AP cores specifically related to verifying and signing of packets received. WDOG Watchdog The Watchdog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. XTAL OSC24M The 24 MHz xtal, when coupled to an external crystal, forms an oscillator which provides one of the two main clock sources to the chip. The OSC24M is used as the reference clock source for all frequency synthesis on the die sourced by PLLs or a cascade thereof. OSC24M can be turned off by the System Control Unit (SCU) during sleep mode. XTAL OSC32K The 32 KHz clock source is an external crystal that is one of two main clock sources to the chip. The OSC32K is intended to be always on and is distributed by the SCU to modules in the chip. 2.1 Special Signal Considerations Special signal considerations can be found in the hardware development guide for this device. Modules List 12 i.MX 8XLite Industrial Applications Processors, Rev. 3, 08/2023 NXP Semiconductors |
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