S12SCIV2SLASHD datasheet(110/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,

typical values are 50.

ζ = 0.9 ensures a good transient response.

And finally the frequency relationship is defined as

With the above inputs the resistance can be calculated as:

The capacitance Cs can now be calculated as:

The capacitance Cp should be chosen in the range of:

The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external

component selection (e.g. crystal, XFC filter).

A.4.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the

deviation from the reference clock fref is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.

Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock

jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.

ζ f

ref

⋅⋅

πζ





⋅

------------------------------------------

------

ref

450

⋅

--------------

ζ 0.9

(

)

;

→

VCO

ref

-------------

synr

()

⋅

π nf

⋅⋅ ⋅

KΦ

-----------------------------

⋅

π f

C R

⋅⋅

----------------------

0.516

C R

⋅

---------------

ζ 0.9

()

;

≈

s 20

⁄

s 10

⁄

≤≤

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S12SCIV2/D Datasheet(PDF) 110 Page - Freescale Semiconductor, Inc

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