S12SCIV2SLASHD datasheet(116/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

Figure A-6 SPI Master Timing (CPHA =1)

Table A-17 SPI Master Mode Timing Characteristics1

NOTES:

1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the

Master and the Slave timing shown in Table A-18.

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Operating Frequency

fop

fbus

1P SCK Period tsck = 1./fop

tsck

2048

tbus

D Enable Lead Time

tlead

/2—

tsck

D Enable Lag Time

tlag

tsck

D Clock (SCK) High or Low Time

twsck

tbus − 30

1024 tbus

D Data Setup Time (Inputs)

tsu

D Data Hold Time (Inputs)

thi

0ns

D Data Valid (after SCK Edge)

D Data Hold Time (Outputs)

tho

0ns

D Rise Time Inputs and Outputs

D Fall Time Inputs and Outputs

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN2

BIT 6 . . . 1

LSB IN

MASTER MSB OUT2

MASTER LSB OUT

BIT 6 . . . 1

PORT DATA

(CPOL

= 0)

(CPOL

= 1)

PORT DATA

SS1

(OUTPUT)

1. If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Freescale Semiconductor, Inc.

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S12SCIV2/D Datasheet(PDF) 116 Page - Freescale Semiconductor, Inc

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