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DSPIC33FJ12MC02ESS Datasheet(PDF) 279 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS Datasheet(HTML) 279 Page - Microchip Technology |
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279 / 284 page  © 2007 Microchip Technology Inc. Preliminary DS70265B-page 277 dsPIC33FJ12MC201/202 Program Memory Interrupt Vector ........................................................... 24 Organization................................................................ 24 Reset Vector ............................................................... 24 Pulse-Width Modulation Mode .......................................... 140 PWM Center-Aligned .......................................................... 148 Complementary Mode............................................... 149 Complementary Output Mode................................... 151 Duty Cycle................................................................. 140 Edge-Aligned ............................................................ 147 Independent Output Mode ........................................ 151 Operation During CPU Idle Mode ............................. 153 Operation During CPU Sleep Mode.......................... 153 Output Override ........................................................ 151 Output Override Synchronization.............................. 151 Period................................................................ 140, 147 Single Pulse Mode .................................................... 151 PWM Dead-Time Generators ........................................... 149 Assignment ............................................................... 150 Ranges...................................................................... 150 Selection Bits (table) ................................................. 150 PWM Duty Cycle Comparison Units ..................................................... 148 Immediate Updates................................................... 149 Register Buffers ........................................................ 148 PWM Fault Pins ................................................................ 151 Enable Bits................................................................ 152 Fault States............................................................... 152 Input Modes .............................................................. 152 Cycle-by-Cycle.................................................. 152 Latched ............................................................. 152 Priority....................................................................... 152 PWM Output and Polarity Control..................................... 151 Output Pin Control .................................................... 151 PWM Special Event Trigger.............................................. 153 Postscaler ................................................................. 153 PWM Time Base ............................................................... 146 Continuous Up/Down Count Modes.......................... 146 Double Update Mode ................................................ 147 Free-Running Mode .................................................. 146 Postscaler ................................................................. 147 Prescaler................................................................... 147 Single-Shot Mode ..................................................... 146 PWM Update Lockout ....................................................... 152 Q QEI 16-bit Up/Down Position Counter Mode.................... 166 Alternate 16-bit Timer/Counter.................................. 167 Count Direction Status .............................................. 166 Error Checking .......................................................... 166 Interrupts................................................................... 168 Logic ......................................................................... 166 Operation During CPU Idle Mode ............................. 167 Operation During CPU Sleep Mode.......................... 167 Position Measurement Mode .................................... 166 Programmable Digital Noise Filters .......................... 167 Timer Operation During CPU Idle Mode ................... 168 Timer Operation During CPU Sleep Mode................ 167 Quadrature Encoder Interface (QEI)................................. 165 Quadrature Encoder Interface (QEI) Module Register Map............................................................... 33 R Reader Response............................................................. 280 Registers AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) .............................................................. 206 ADxCHS0 (ADCx Input Channel 0 Select ................ 208 ADxCON1 (ADCx Control 1) .................................... 202 ADxCON2 (ADCx Control 2) .................................... 204 ADxCON3 (ADCx Control 3) .................................... 205 ADxCSSL (ADCx Input Scan Select Low)................ 209 ADxPCFGL (ADCx Port Configuration Low) ............ 210 CLKDIV (Clock Divisor) .............................................. 98 CORCON (Core Control)...................................... 16, 66 DFLTCON (QEI Control) .......................................... 171 I2CxCON (I2Cx Control)........................................... 185 I2CxMSK (I2Cx Slave Mode Address Mask)............ 189 I2CxSTAT (I2Cx Status) ........................................... 187 IEC0 (Interrupt Enable Control 0) ............................... 75 IEC1 (Interrupt Enable Control 1) ............................... 77 IEC3 (Interrupt Enable Control 3) ............................... 78 IEC4 (Interrupt Enable Control 4) ............................... 79 IFS0 (Interrupt Flag Status 0) ..................................... 70 IFS1 (Interrupt Flag Status 1) ..................................... 72 IFS3 (Interrupt Flag Status 3) ..................................... 73 IFS4 (Interrupt Flag Status 4) ..................................... 74 INTCON1 (Interrupt Control 1) ................................... 67 INTCON2 (Interrupt Control 2) ................................... 69 INTTREG Interrupt Control and Status Register ........ 90 IPC0 (Interrupt Priority Control 0) ............................... 80 IPC1 (Interrupt Priority Control 1) ............................... 81 IPC14 (Interrupt Priority Control 14) ........................... 87 IPC15 (Interrupt Priority Control 15) ........................... 88 IPC16 (Interrupt Priority Control 16) ........................... 88 IPC18 (Interrupt Priority Control 18) ........................... 89 IPC2 (Interrupt Priority Control 2) ............................... 82 IPC3 (Interrupt Priority Control 3) ............................... 83 IPC4 (Interrupt Priority Control 4) ............................... 84 IPC5 (Interrupt Priority Control 5) ............................... 85 IPC7 (Interrupt Priority Control 7) ............................... 86 NVMCON (Flash Memory Control)............................. 51 NVMKEY (Nonvolatile Memory Key) .......................... 52 OCxCON (Output Compare x Control) ..................... 142 OSCCON (Oscillator Control)..................................... 96 OSCTUN (FRC Oscillator Tuning)............................ 100 P1DC3 (PWM Duty Cycle 3) .................................... 164 PLLFBD (PLL Feedback Divisor) ............................... 99 PWMxCON1 (PWM Control 1) ................................. 157 PWMxCON2 (PWM Control 2) ................................. 158 PxDC1 (PWM Duty Cycle 1)..................................... 163 PxDC2 (PWM Duty Cycle 2)..................................... 163 PxDTCON1 (Dead-Time Control 1).......................... 159 PxDTCON2 (Dead-Time Control 2).......................... 160 PxFLTACON (Fault A Control) ................................. 161 PxOVDCON (Override Control)................................ 162 PxSECMP (Special Event Compare) ....................... 156 PxTCON (PWM Time Base Control) ........................ 154 PxTMR (PWM Timer Count Value) .......................... 155 PxTPER (PWM Time Base Period) .......................... 155 QEICON (QEI Control) ............................................. 169 RCON (Reset Control)................................................ 56 SPIxCON1 (SPIx Control 1) ..................................... 178 SPIxCON2 (SPIx Control 2) ..................................... 180 SPIxSTAT (SPIx Status and Control) ....................... 177 SR (CPU Status) .................................................. 14, 66 T1CON (Timer1 Control) .......................................... 130 |
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