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CLRC63201T/0FE Datasheet(PDF) 154 Page - NXP Semiconductors |
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CLRC63201T/0FE Datasheet(HTML) 154 Page - NXP Semiconductors |
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154 / 163 page  Philips Semiconductors Product Specification Rev. 3.0; May 2003 Multiple Protocol Contactless Reader IC CL RC632 154 Confidential 22.5.2.2 Bus Timing for Common Read/Write Strobe SYMBOL PARAMETER MIN MAX UNIT tLHLL AS pulse width 20 ns tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 15 ns tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 8 ns tLLSL AS low to NDS low 15 ns tCLSL NCS low to NDS low 0 ns tSHCH NDS high to NCS high 0 ns tSLDV,R NDS low to DATA valid (for read cycle) 65 ns tSHDZ NDS low to DATA high impedance (read cycle) 20 ns tSLDV,W NDS low to DATA valid (for write cycle) 35 ns tSHDX DATA hold after NDS high (write cycle, Hold Time) 8 ns tSHRX R/NW hold after NDS high 8 ns tSLSH NDS pulse width 65 ns tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 ns tSHAX Separated Address Bus valid after NDS high (Set Up Time) 8 ns tSHSL period between sequenced read/write accesses 150 ns tRVSL R/NW valid to NDS low 8 ns Table 22-11: Timing Specification for Common Read/Write Strobe Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3. t AVLL ALE t LHLL NCS t CLSL t SHDX t SHDZ D0 ... D7 D0 ... D7 t SLDV,R t SLDV,W t LLAX t SHSL NDS t SLSH t LLSL t SHSL A0 ... A2 t AVSL Multiplexed Addressbus A0 ... A2 t SHAX Separated Addressbus A0 ... A2 t RVSL R/NW t SHCH t SHRX Figure 22-2: Timing Diagram for Common Read/Write Strobe |
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