PIC18F44J10-ESLASHSP datasheet(249/358 Pages) MICROCHIP

249 / 358 page

Preliminary

DS39682C-page 247

PIC18F45J10 FAMILY

21.1.1

STANDARD INSTRUCTION SET

ADDLW

ADD Literal to W

Syntax:

ADDLW

Operands:

≤ k ≤ 255

Operation:

(W) + k

→ W

Status Affected:

N, OV, C, DC, Z

Encoding:

0000

1111

kkkk

Description:

The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

ADDLW

15h

Before Instruction

10h

After Instruction

25h

ADDWF

ADD W to f

Syntax:

ADDWF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) + (f)

→ dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0010

01da

ffff

Description:

Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

ADDWF

REG,

0, 0

Before Instruction

17h

REG

0C2h

After Instruction

0D9h

REG

0C2h

Note:

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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