PIC18F44J10-ESLASHML datasheet(250/358 Pages) MICROCHIP

250 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 248

Preliminary

ADDWFC

ADD W and Carry bit to f

Syntax:

ADDWFC

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) + (f) + (C)

→ dest

Status Affected:

N,OV, C, DC, Z

Encoding:

0010

00da

ffff

Description:

Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

ADDWFC

REG,

0, 1

Before Instruction

Carry bit

REG

02h

4Dh

After Instruction

Carry bit

REG

02h

50h

ANDLW

AND Literal with W

Syntax:

ANDLW

Operands:

≤ k ≤ 255

Operation:

(W) .AND. k

→ W

Status Affected:

N, Z

Encoding:

0000

1011

kkkk

Description:

The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

‘k’

Process

Data

Write to W

Example:

ANDLW

05Fh

Before Instruction

A3h

After Instruction

03h

PIC18F44J10-E/ML Datasheet(PDF) 250 Page - Microchip Technology

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