PIC18F44J10-ESLASHML datasheet(277/358 Pages) MICROCHIP

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Preliminary

DS39682C-page 275

PIC18F45J10 FAMILY

RRNCF

Rotate Right f (No Carry)

Syntax:

RRNCF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f<n>)

→ dest<n – 1>,

(f<0>)

→ dest<7>

Status Affected:

N, Z

Encoding:

0100

00da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

RRNCF

REG, 1, 0

Before Instruction

REG

1101 0111

After Instruction

REG

1110 1011

Example 2:

RRNCF

REG, 0, 0

Before Instruction

REG

1101 0111

After Instruction

1110 1011

REG

1101 0111

SETF

Set f

Syntax:

SETF

f {,a}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

FFh

→ f

Status Affected:

None

Encoding:

0110

100a

ffff

Description:

The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

SETF

REG, 1

Before Instruction

REG

5Ah

After Instruction

REG

FFh

PIC18F44J10-E/ML Datasheet(PDF) 277 Page - Microchip Technology

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