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PIC18F44J10-E/ML Datasheet(PDF) 352 Page - Microchip Technology |
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PIC18F44J10-E/ML Datasheet(HTML) 352 Page - Microchip Technology |
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352 / 358 page  PIC18F45J10 FAMILY DS39682C-page 350 Preliminary © 2007 Microchip Technology Inc. Timing Diagrams A/D Conversion ......................................................... 326 Acknowledge Sequence ........................................... 179 Asynchronous Reception .......................................... 200 Asynchronous Transmission ..................................... 198 Asynchronous Transmission (Back to Back) ............ 198 Automatic Baud Rate Calculation ............................. 196 Auto-Wake-up Bit (WUE) During Normal Operation . 201 Auto-Wake-up Bit (WUE) During Sleep .................... 201 Baud Rate Generator with Clock Arbitration ............. 173 BRG Overflow Sequence .......................................... 196 BRG Reset Due to SDAx Arbitration During Start Condition........................................................... 182 Brown-out Reset (BOR) ............................................ 314 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 183 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 183 Bus Collision During a Start Condition (SCLx = 0).... 182 Bus Collision During a Stop Condition (Case 1) ....... 184 Bus Collision During a Stop Condition (Case 2) ....... 184 Bus Collision During Start Condition (SDAx Only) .... 181 Bus Collision for Transmit and Acknowledge............ 180 Capture/Compare/PWM (Including ECCP Module) .. 316 CLKO and I/O ........................................................... 313 Clock Synchronization .............................................. 166 Clock/Instruction Cycle ............................................... 51 EUSART Synchronous Receive (Master/Slave) ....... 325 EUSART Synchronous Transmission (Master/Slave)................................................... 325 Example SPI Master Mode (CKE = 0) ...................... 317 Example SPI Master Mode (CKE = 1) ...................... 318 Example SPI Slave Mode (CKE = 0) ........................ 319 Example SPI Slave Mode (CKE = 1) ........................ 320 External Clock (All Modes Except PLL) .................... 311 Fail-Safe Clock Monitor............................................. 239 First Start Bit Timing ................................................. 174 Full-Bridge PWM Output ........................................... 137 Half-Bridge PWM Output .......................................... 136 I2C Bus Data ............................................................. 321 I2C Bus Start/Stop Bits.............................................. 321 I2C Master Mode (7 or 10-Bit Transmission) ............ 177 I2C Master Mode (7-Bit Reception) ........................... 178 I2C Slave Mode (10-Bit Reception, SEN = 0) ........... 163 I2C Slave Mode (10-Bit Reception, SEN = 1) ........... 168 I2C Slave Mode (10-Bit Transmission)...................... 164 I2C Slave Mode (7-bit Reception, SEN = 0).............. 161 I2C Slave Mode (7-Bit Reception, SEN = 1) ............. 167 I2C Slave Mode (7-Bit Transmission)........................ 162 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ....................................... 169 I2C Stop Condition Receive or Transmit Mode ......... 179 Master SSP I2C Bus Data ......................................... 323 Master SSP I2C Bus Start/Stop Bits ......................... 323 Parallel Slave Port (PSP) Read ................................ 110 Parallel Slave Port (PSP) Write ................................ 110 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Dis- abled) ................................................................ 142 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart En- abled) ................................................................ 142 PWM Direction Change ............................................ 139 PWM Direction Change at Near 100% Duty Cycle ... 139 PWM Output ............................................................. 128 Repeated Start Condition.......................................... 175 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................ 314 Send Break Character Sequence ............................. 202 Slave Synchronization .............................................. 151 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................. 41 SPI Mode (Master Mode).......................................... 150 SPI Mode (Slave Mode, CKE = 0) ............................ 152 SPI Mode (Slave Mode, CKE = 1) ............................ 152 Synchronous Reception (Master Mode, SREN) ....... 205 Synchronous Transmission ...................................... 203 Synchronous Transmission (Through TXEN) ........... 204 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 .......................................... 40 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 .......................................... 41 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise Tpwrt) ......................................... 40 Timer0 and Timer1 External Clock ........................... 315 Transition for Entry to Idle Mode................................. 35 Transition for Entry to SEC_RUN Mode ..................... 32 Transition for Entry to Sleep Mode ............................. 34 Transition for Two-Speed Start-up (INTRC) ............. 237 Transition for Wake from Idle to Run Mode ................ 35 Transition for Wake from Sleep .................................. 34 Transition from RC_RUN Mode to PRI_RUN Mode ... 33 Transition to RC_RUN Mode ...................................... 33 Timing Diagrams and Specifications A/D Conversion Requirements ................................. 327 AC Characteristics Internal RC Accuracy........................................ 312 Capture/Compare/PWM Requirements (Including ECCP Module).................................................. 316 CLKO and I/O Requirements.................................... 313 EUSART Synchronous Receive Requirements........ 325 EUSART Synchronous Transmission Requirements 325 Example SPI Mode Requirements (Master Mode, CKE = 0) ........................................................... 317 Example SPI Mode Requirements (Master Mode, CKE = 1) ........................................................... 318 Example SPI Mode Requirements (Slave Mode, CKE = 0) ........................................................... 319 Example SPI Slave Mode Requirements (CKE = 1). 320 External Clock Requirements ................................... 311 I2C Bus Data Requirements (Slave Mode) ............... 322 I2C Bus Start/Stop Bits Requirements (Slave Mode) 321 Master SSP I2C Bus Data Requirements ................. 324 Master SSP I2C Bus Start/Stop Bits Requirements.. 323 Parallel Slave Port Requirements............................. 316 PLL Clock ................................................................. 312 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................................................... 314 Timer0 and Timer1 External Clock Requirements.... 315 Top-of-Stack Access........................................................... 48 TRISE Register PSPMODE Bit........................................................... 103 TSTFSZ ............................................................................ 281 Two-Speed Start-up.................................................. 229, 237 Two-Word Instructions Example Cases........................................................... 52 TXSTA Register BRGH Bit .................................................................. 191 |
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