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PIC18F4685-I/SP Datasheet(PDF) 279 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 279 Page - Microchip Technology |
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279 / 484 page  © 2007 Microchip Technology Inc. Preliminary DS39761B-page 277 PIC18F2682/2685/4682/4685 REGISTER 23-2: CANSTAT: CAN STATUS REGISTER Mode 0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) — ICODE3 ICODE2 ICODE1 — Mode 1,2 R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode bit 4 Mode 0: Unimplemented: Read as ‘0’ bit 3-1 ICODE3:ICODE1: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE3:ICODE1 to WIN2:WIN0 (Mode 0) or EICODE4:EICODE0 to EWIN4:EWIN0 (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code example. To simplify the description, the following table lists all five bits. bit 0 Unimplemented: Read as ‘0’ bit 4-0 Mode 1, 2: EICODE4:EICODE0: Interrupt Code bits See ICODE3:ICODE1 above. Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module in Disable mode before putting device to Sleep. 2: If buffer is configured as receiver, EICODE bits will contain ‘10000’ upon interrupt. Mode 0 Mode 1 Mode 2 No interrupt 00000 00000 00000 Error interrupt 00010 00010 00010 TXB2 interrupt 00100 00100 00100 TXB1 interrupt 00110 00110 00110 TXB0 interrupt 01000 01000 01000 RXB1 interrupt 01010 10001 ----- RXB0 interrupt 01100 10000 10000 Wake-up interrupt 00010 01110 01110 RXB0 interrupt ----- 10000 10000 RXB1 interrupt ----- 10001 10000 RX/TX B0 interrupt ----- 10010 10010 RX/TX B1 interrupt ----- 10011 10011(2) RX/TX B2 interrupt ----- 10100 10100(2) RX/TX B3 interrupt ----- 10101 10101(2) RX/TX B4 interrupt ----- 10110 10110(2) RX/TX B5 interrupt ----- 10111 10111(2) |
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