PIC18F4685-ISLASHSP datasheet(290/484 Pages) MICROCHIP

290 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 288

Preliminary

23.2.3

DEDICATED CAN RECEIVE

BUFFER REGISTERS

This section shows the dedicated CAN Receive Buffer

registers with their associated control registers.

Mode 0

R/C-0

R/W-0

U-0

R-0

R/W-0

R-0

RXFUL(1)

RXM1

RXM0

—

RXRTRRO RXB0DBEN

JTOFF(2)

FILHIT0

Mode 1,2

R/C-0

R/W-0

R-0

RXFUL(1)

RXM1

RTRRO

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

bit 7

bit 0

Legend:

C = Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RXFUL: Receive Full Status bit(1)

= Receive buffer contains a received message

= Receive buffer is open to receive a new message

bit 6

Mode 0:

RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5)

= Receive all messages (including those with errors); filter criteria is ignored

= Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’

= Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be ‘0’

= Receive all valid messages as per EXIDEN bit in RXFnSIDL register

Mode 1, 2:

RXM1: Receive Buffer Mode bit 1

= Receive all messages (including those with errors); acceptance filters are ignored

= Receive all valid messages as per acceptance filters

bit 5

Mode 0:

RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6)

Mode 1, 2:

RTRRO: Remote Transmission Request bit for Received Message (read-only)

= A remote transmission request is received

= A remote transmission request is not received

bit 4

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

FILHIT4: Filter Hit bit 4

This bit combines with other bits to form filter acceptance bits <4:0>.

bit 3

Mode 0:

RXRTRRO: Remote Transmission Request bit for Received Message (read-only)

= A remote transmission request is received

= A remote transmission request is not received

Mode 1, 2:

FILHIT3: Filter Hit bit 3

This bit combines with other bits to form filter acceptance bits <4:0>.

Note 1:

This bit is set by the CAN module upon receiving a message and must be cleared by software after the

buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.

After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is

not cleared, then RXB0IF is set again.

This bit allows same filter jump table for both RXB0CON and RXB1CON.

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