PIC18F4685-ISLASHSP datasheet(384/484 Pages) MICROCHIP

384 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 382

Preliminary

DAW

Decimal Adjust W Register

Syntax:

DAW

Operands:

None

Operation:

If [W<3:0> >9] or [DC = 1] then

(W<3:0>) + 6

→ W<3:0>;

else

(W<3:0>)

→ W<3:0>

If [W<7:4> >9] or [C = 1] then

(W<7:4>) + 6

→ W<7:4>;

C = 1;

else

(W<7:4>)

→ W<7:4>

Status Affected:

Encoding:

0000

0111

Description:

DAW

adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example 1:

DAW

Before Instruction

A5h

After Instruction

05h

Example 2:

Before Instruction

CEh

After Instruction

34h

DECF

Decrement f

Syntax:

DECF f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) – 1

→ dest

Status Affected:

C, DC, N, OV, Z

Encoding:

0000

01da

ffff

Description:

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

DECF

CNT,

1, 0

Before Instruction

CNT

01h

After Instruction

CNT

00h

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