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PIC18F4685-I/SP Datasheet(PDF) 452 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 452 Page - Microchip Technology |
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452 / 484 page ![]() PIC18F2682/2685/4682/4685 DS39761B-page 450 Preliminary © 2007 Microchip Technology Inc. FIGURE 27-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 27-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 27-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS 121 121 120 122 RC6/TX/CK RC7/RX/DT pin pin Note: Refer to Figure 27-4 for load conditions. Param No. Symbol Characteristic Min Max Units Conditions 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V 125 126 RC6/TX/CK RC7/RX/DT pin pin Note: Refer to Figure 27-4 for load conditions. Param. No. Symbol Characteristic Min Max Units Conditions 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns |
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