PIC18F4685-ISLASHSP datasheet(145/484 Pages) MICROCHIP

145 / 484 page

Preliminary

DS39761B-page 143

PIC18F2682/2685/4682/4685

TABLE 10-9:

PORTE I/O SUMMARY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Pin Name

Function

I/O

TRIS Buffer

Description

RE0/RD/AN5

RE0

OUT

DIG

LATE<0> data output.

PORTE<0> data input.

TTL

PSP read enable input.

AN5

ANA

A/D input channel 5. Enabled on POR, this analog input overrides the

digital input (read as clear – low level).

RE1/WR/AN6/C1OUT RE1

OUT

DIG

LATE<1> data output.

PORTE<1> data input.

TTL

PSP write enable input.

AN6

ANA

A/D input channel 6. Enabled on POR, this analog input overrides the

digital input (read as clear – low level).

C1OUT

OUT

DIG

Comparator 1 output.

RE2/CS/AN7/C2OUT

RE2

OUT

DIG

LATE<2> data output.

PORTE<2> data input.

TTL

PSP chip select input.

AN7

ANA

A/D input channel 7. Enabled on POR, this analog input overrides the

digital input (read as clear – low level).

C2OUT

OUT

DIG

Comparator 2 output.

MCLR/VPP/RE3

MCLR

External Reset input. Disabled when MCLRE Configuration bit is ‘1’.

VPP

ANA

High-voltage detection; used by ICSP™ operation.

RE3

PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.

Legend:

OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTE(3)

—

—RE3(1,2)

RE2

RE1

RE0

LATE(3)

—

LATE Data Output Register

TRISE(3)

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

CMCON(3)

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1:

Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

RE3 is the only PORTE bit implemented on both PIC18F2682/2685 and PIC18F4682/4685 devices. All

other bits are implemented only when PORTE is implemented (i.e., PIC18F4682/4685 devices).

These registers are unimplemented on PIC18F2682/2685 devices.

PIC18F4685-I/SP Datasheet(PDF) 145 Page - Microchip Technology

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