PIC18F4685-ISLASHSP datasheet(150/484 Pages) MICROCHIP

150 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 148

Preliminary

11.1

Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode

selected

clearing

the

T0CS

bit

(T0CON<5>). In Timer mode, the module increments

on every clock by default unless a different prescaler

value is selected (see Section 11.3 “Prescaler”). If

the TMR0 register is written to, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

The Counter mode is selected by setting the T0CS bit

(= 1). In Counter mode, Timer0 increments either on

every rising or falling edge of pin RA4/T0CKI. The

incrementing edge is determined by the Timer0 Source

Edge Select bit, T0SE (T0CON<4>). Clearing this bit

selects the rising edge. Restrictions on the external

clock input are discussed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

internal phase clock (TOSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.2

Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0, which is not directly readable nor

writable (refer to Figure 11-2). TMR0H is updated with

the contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte were valid, due to a rollover between

successive reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

FIGURE 11-1:

TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2:

TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

Programmable

Prescaler

Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

Programmable

Prescaler

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