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PIC16F946-E/MLQTP Datasheet(PDF) 284 Page - Microchip Technology

Part # PIC16F946-E/MLQTP
Description  28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
PDF  330 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F946-E/MLQTP Datasheet(HTML) 284 Page - Microchip Technology

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PIC16F913/914/916/917/946
DS41250F-page 282
© 2007 Microchip Technology Inc.
TABLE 19-16: I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
100*
THIGH
Clock high time
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
101*
TLOW
Clock low time
400 kHz mode
1.3
—
μs
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
102*
TR
SDA and SCL rise
time
400 kHz mode
20 + 0.1CB
250
ns
CB is specified to be from
10-400 pF
103*
TF
SDA and SCL fall time 400 kHz mode
20 + 0.1CB
250
ns
CB is specified to be from
10-400 pF
90*
TSU:STA
Start condition setup
time
400 kHz mode
1.3
—
μs
Only relevant for Repeated
Start condition
91*
THD:STA
Start condition hold
time
400 kHz mode
0.6
—
μs
After this period the first clock
pulse is generated
106*
THD:DAT
Data input hold time
400 kHz mode
0
0.9
μs
107*
TSU:DAT
Data input setup time 400 kHz mode
100
—
ns
(Note 2)
92*
TSU:STO
Stop condition setup
time
400 kHz mode
0.6
—
μs
109*
TAA
Output valid from
clock
400 kHz mode
—
—
ns
(Note 1)
110*
TBUF
Bus free time
400 kHz mode
1.3
—
μs
Time the bus must be free
before a new transmission
can start
CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT
≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.



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