PIC16F946-ESLASHMLQTP datasheet(120/330 Pages) MICROCHIP

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PIC16F913/914/916/917/946

DS41250F-page 118

8.10

Comparator Voltage Reference

The Comparator Voltage Reference module provides

an internally generated voltage reference for the com-

parators. The following features are available:

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

• Ratiometric with VDD

The VRCON register (Register 8-3) controls the

Voltage Reference module shown in Figure 8-8.

8.10.1

INDEPENDENT OPERATION

The comparator voltage reference is independent of

the comparator configuration. Setting the VREN bit of

the VRCON register will enable the voltage reference.

8.10.2

OUTPUT VOLTAGE SELECTION

The

CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

The CVREF output voltage is determined by the following

equations:

EQUATION 8-1:

CVREF OUTPUT VOLTAGE

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 8-8.

8.10.3

OUTPUT CLAMPED TO VSS

The CVREF output voltage can be set to Vss with no

power consumption by configuring VRCON as follows:

•VREN = 0

•VRR = 1

•VR<3:0> = 0000

This allows the comparator to detect a zero-crossing

while not consuming additional CVREF module current.

8.10.4

OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 19.0

“Electrical Specifications”.

VRR

1 (low range):

VRR

0 (high range):

CVREF

(VDD/4) +

CVREF

(VR<3:0>/24) VDD

(VR<3:0> VDD/32)

VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

VREN

—VRR

—

VR3

VR2

VR1

VR0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

VREN: CVREF Enable bit

= CVREF circuit powered on

= CVREF circuit powered down, no IDD drain and CVREF = VSS.

bit 6

Unimplemented: Read as ‘0’

bit 5

VRR: CVREF Range Selection bit

= Low range

= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: CVREF Value Selection bits (0

≤ VR<3:0> ≤ 15)

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

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