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PIC16F946-E/MLQTP Datasheet(PDF) 142 Page - Microchip Technology |
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PIC16F946-E/MLQTP Datasheet(HTML) 142 Page - Microchip Technology |
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142 / 330 page  PIC16F913/914/916/917/946 DS41250F-page 140 © 2007 Microchip Technology Inc. 9.3.2.3 AUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 9.3.1.4 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE interrupt enable bit of the PIE1 register is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 9.3.2.4 Synchronous Slave Reception Set-up: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 3. If 9-bit reception is desired, set the RX9 bit. 4. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. 5. Set the CREN bit to enable reception. 6. The RCIF bit of the PIR1 register will be set when reception is complete. An interrupt will be generated if the RCIE bit of the PIE1 register was set. 7. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register. TABLE 9-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000 PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCREG AUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. |
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