DSPIC30F2010AT-20ESLASHSP datasheet(102/203 Pages) MICROCHIP

102 / 203 page

dsPIC30F2010

DS70118G-page 100

16.12.1

I2C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address or the sec-

ond half of a 10-bit address is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a Wait

state. This action will set the buffer full flag (TBF) and

allow the Baud Rate Generator to begin counting and

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

16.12.2

I2C MASTER RECEPTION

Master mode reception is enabled by programming the

receive enable (RCEN) bit (I2CCON<11>). The I2C

module must be Idle before the RCEN bit is set, other-

wise the RCEN bit will be disregarded. The Baud Rate

Generator begins counting, and on each rollover, the

state of the SCL pin toggles, and data is shifted in to the

I2CRSR on the rising edge of each clock.

16.12.3

BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock

arbitration is taking place, for instance, the BRG is

reloaded when the SCL pin is sampled high.

As per the I2C standard, FSCK may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 16-1:

I2CBRG VALUE

16.12.4

CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCL pin is allowed to float high, the Baud Rate

Generator is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the contents of I2CBRG and begins counting. This

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

16.12.5

MULTI-MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master operation support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA, by letting SDA float high

while another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2CIF pulse and reset the master

portion of the I2C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are de-asserted, and a

value can now be written to I2CTRN. When the user

services the I2C master event Interrupt Service

Routine, if the I2C bus is free (i.e., the P bit is set) the

user can resume communication by asserting a Start

condition.

If a Start, Restart, Stop or Acknowledge condition was

in progress when the bus collision occurred, the condi-

tion is aborted, the SDA and SCL lines are de-asserted,

and the respective control bits in the I2CCON register

are cleared to ‘0’. When the user services the bus col-

lision Interrupt Service Routine, and if the I2C bus is

free, the user can resume communication by asserting

a Start condition.

The Master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTRN will start the transmission of data

at the first data bit, regardless of where the transmitter

left off when bus collision occurred.

In a Multi-Master environment, the interrupt generation

on the detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the I2CSTAT

cleared.

I2CBRG

Fcy

Fscl

-----------

Fcy

1 111 111

---------------------------

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DSPIC30F2010AT-20E/SP Datasheet(PDF) 102 Page - Microchip Technology

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