PIC18F23K20-ESLASHPSQTP datasheet(214/420 Pages) MICROCHIP

214 / 420 page

PIC18F2XK20/4XK20

DS41303B-page 212

Advance Information

17.4.7

BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the SSPADD register

(Figure 17-17). When a write occurs to SSPBUF, the

Baud Rate Generator will automatically begin counting.

The BRG counts down to ‘0’ and stops until another

reload has taken place. The BRG count is decre-

mented twice per instruction cycle (TCY) on the Q2 and

Q4 clocks. In I2C Master mode, the BRG is reloaded

automatically. One half of the SCL period is equal to

[(SSPADD+1)

• 2]/FOSC. Therefore SSPADD =

(FCY/FSCL) -1.

Once

the

given

operation

complete

(i.e.,

transmission of the last data bit is followed by ACK), the

internal clock will automatically stop counting and the

SCL pin will remain in its last state.

Table 17-3

demonstrates

clock

rates

based

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 17-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 17-3:

I2C™ CLOCK RATE W/BRG

SSPM<3:0>

BRG Down Counter

CLKOUT

FOSC/2

SSPADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

FOSC

FCY

BRG Value

FSCL

(2 Rollovers of BRG)

64 MHz

16 MHz

27h

400 kHz(1)

64 MHz

16 MHz

32h

313.7 kHz

64 MHz

16 MHz

3Fh

250 kHz

40 MHz

10 MHz

18h

400 kHz(1)

40 MHz

10 MHz

1Fh

312.5 kHz

40 MHz

10 MHz

63h

100 kHz

16 MHz

4 MHz

09h

400 kHz(1)

16 MHz

4 MHz

0Ch

308 kHz

16 MHz

4 MHz

27h

100 kHz

4 MHz

1 MHz

02h

333 kHz(1)

4 MHz

1 MHz

09h

100 kHz

4 MHz

1 MHz

00h

1 MHz(1)

Note 1:

The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

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