PIC18F23K20-ESLASHML datasheet(216/420 Pages) MICROCHIP

216 / 420 page

PIC18F2XK20/4XK20

DS41303B-page 214

Advance Information

17.4.8

I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPCON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator

reloaded

with

the

contents

SSPADD<6:0> and starts its count. If SCL and SDA are

both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT1

ator is reloaded with the contents of SSPADD<6:0>

and resumes its count. When the Baud Rate Generator

times out (TBRG), the SEN bit of the SSPCON2 register

will be automatically cleared by hardware; the Baud

Rate Generator is suspended, leaving the SDA line

held low and the Start condition is complete.

17.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 17-19:

FIRST START BIT TIMING

Note:

If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I2C module is reset into its Idle state.

Note:

Because queueing of events

not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

condition is complete.

SDA

SCL

TBRG

1st bit

2nd bit

TBRG

SDA = 1,

At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPSTAT<3>)

and sets SSPIF bit

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