PIC18F23K20-ESLASHML datasheet(241/420 Pages) MICROCHIP

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Advance Information

DS41303B-page 239

PIC18F2XK20/4XK20

18.3

EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCTL register selects 16-bit

mode.

The SPBRGH:SPBRG register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

Synchronous mode, the BRGH bit is ignored.

Table 18-3 contains the formulas for determining the

baud rate. Example 18-1 provides a sample calculation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 18-5. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

Writing a new value to the SPBRGH, SPBRG register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

EXAMPLE 18-1:

CALCULATING BAUD

RATE ERROR

TABLE 18-3:

BAUD RATE FORMULAS

TABLE 18-4:

REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

Solving for SPBRGH:SPBRG:

FOSC

Desired Baud Rate

---------------------------------------------

–

Desired Baud Rate

FOSC

64 [SPBRGH:SPBRG]

()

---------------------------------------------------------------------

16000000

9600

------------------------

–

25.042

[]

Calculated Baud Rate

16000000

64 25

()

---------------------------

9615

Error

Calc. Baud Rate

Desired Baud Rate

–

Desired Baud Rate

--------------------------------------------------------------------------------------------

9615

9600

–

()

9600

----------------------------------

0.16%

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

SYNC

BRG16

BRGH

8-bit/Asynchronous

FOSC/[64 (n+1)]

8-bit/Asynchronous

FOSC/[16 (n+1)]

16-bit/Asynchronous

FOSC/[4 (n+1)]

8-bit/Synchronous

16-bit/Synchronous

Legend:

= Don’t care, n = value of SPBRGH, SPBRG register pair

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values

on page

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

BAUDCTL

ABDOVF

RCIDL

DTRXP

CKTXP

BRG16

—

WUE

ABDEN

SPBRGH

EUSART Baud Rate Generator Register, High Byte

SPBRG

EUSART Baud Rate Generator Register, Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

PIC18F23K20-E/ML Datasheet(PDF) 241 Page - Microchip Technology

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