PIC18F23K20-ESLASHML datasheet(285/420 Pages) MICROCHIP

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Advance Information

DS41303B-page 283

PIC18F2XK20/4XK20

22.0

HIGH/LOW-VOLTAGE

DETECT (HLVD)

PIC18F2XK20/4XK20 devices have a High/Low-Voltage

Detect module (HLVD). This is a programmable circuit

that allows the user to specify both a device voltage trip

point and the direction of change from that point. If the

device experiences an excursion past the trip point in

that direction, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the inter-

rupt vector address and the software can then respond

to the interrupt.

The

High/Low-Voltage

Detect

Control

(Register 22-1) completely controls the operation of the

HLVD module. This allows the circuitry to be “turned

off” by the user under software control, which

minimizes the current consumption for the device.

The block diagram for the HLVD module is shown in

Figure 22-1.

The module is enabled by setting the HLVDEN bit.

Each time that the HLVD module is enabled, the cir-

cuitry requires some time to stabilize. The IRVST bit is

a read-only bit and is used to indicate when the circuit

is stable. The module can only generate an interrupt

after the circuit is stable and IRVST is set.

The VDIRMAG bit determines the overall operation of

the module. When VDIRMAG is cleared, the module

monitors for drops in VDD below a predetermined set

point. When the bit is set, the module monitors for rises

in VDD above the set point.

HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0

U-0

R-0

R/W-0

R/W-1

R/W-0

R/W-1

VDIRMAG

—

IRVST

HLVDEN

HLVDL3(1)

HLVDL2(1)

HLVDL1(1)

HLVDL0(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented

C = Clearable only bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

VDIRMAG: Voltage Direction Magnitude Select bit

= Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)

= Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)

bit 6

Unimplemented: Read as ‘0’

bit 5

IRVST: Internal Reference Voltage Stable Flag bit

= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range

= Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage

range and the HLVD interrupt should not be enabled

bit 4

HLVDEN: High/Low-Voltage Detect Power Enable bit

= HLVD enabled

= HLVD disabled

bit 3-0

HLVDL<3:0>: Voltage Detection Limit bits(1)

1111

= External analog input is used (input comes from the HLVDIN pin)

1110

= Maximum setting

0000

= Minimum setting

Note 1:

See Table 26-3 for specifications.

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