PIC18F23K20-ESLASHML datasheet(302/420 Pages) MICROCHIP

302 / 420 page

PIC18F2XK20/4XK20

DS41303B-page 300

Advance Information

23.3

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC® microcontroller devices.

The user program memory is divided into five blocks.

One of these is a boot block of 0.5K or 2K bytes,

depending on the device. The remainder of the mem-

ory is divided into individual blocks on binary bound-

aries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 23-2 shows the program memory organization

for 8, 16 and 32-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 23-3.

FIGURE 23-2:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2XK20/4XK20

TABLE 23-3:

SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—CP3(1)

CP2(1)

CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

30000Ah

CONFIG6L

—

—WRT3(1)

WRT2(1)

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

30000Ch

CONFIG7L

—

EBTR3(1)

EBTR2(1)

EBTR1

EBTR0

30000Dh

CONFIG7H

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1:

Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

8Kbytes

(PIC18FX3K20)

16 Kbytes

(PIC18FX4K20)

32 Kbytes

(PIC18FX5K20)

64 Kbytes

(PIC18FX6K20)

Boot Block

(000h-1FFh)

Boot Block

(000h-7FFh)

Boot Block

(000h-7FFh)

Boot Block

(000h-7FFh)

CPB, WRTB, EBTRB

Block 0

(200h-FFFh)

Block 0

(800h-1FFFh)

Block 0

(800h-1FFFh)

Block 0

(800h-3FFFh)

CP0, WRT0, EBTR0

Block 1

(1000h-1FFFh)

Block 1

(2000h-3FFFh)

Block 1

(2000h-3FFFh)

Block 1

(4000h-7FFFh)

CP1, WRT1, EBTR1

Unimplemented

Read ‘0’s

(2000h-1FFFFFh)

Unimplemented

Read ‘0’s

(4000h-1FFFFFh)

Block 2

(4000h-5FFFh)

Block 2

(8000h-BFFFh)

CP2, WRT2, EBTR2

Block 3

(6000h-7FFFh)

Block 3

(C000h-FFFFh)

CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

(8000h-1FFFFFh)

Unimplemented

Read ‘0’s

(10000h-1FFFFFh)

(Unimplemented

Memory Space)

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