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PIC18F23K20-E/ML Datasheet(PDF) 379 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 379 Page - Microchip Technology |
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379 / 420 page  © 2007 Microchip Technology Inc. Advance Information DS41303B-page 377 PIC18F2XK20/4XK20 TABLE 26-9: CLKOUT AND I/O TIMING REQUIREMENTS FIGURE 26-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING Param No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 ↑ to CLKOUT ↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1 ↑ to CLKOUT ↑ — 75 200 ns (Note 1) 12 TckR CLKOUT Rise Time — 35 100 ns (Note 1) 13 TckF CLKOUT Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKOUT ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKOUT ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKOUT ↑ 0— — ns (Note 1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) 100 — — ns 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time — 10 25 ns 21 TioF Port Output Fall Time — 10 25 ns 22† TINP INT pin High or Low Time TCY —— ns 23† TRBP RB7:RB4 Change INT High or Low Time TCY —— ns 24† TRCP RC7:RC4 Change INT High or Low Time 20 ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC. VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 33 32 30 31 34 I/O pins 34 Note: Refer to Figure 26-3 for load conditions. |
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