PIC18F258-ESLASHLSQTP datasheet(258/402 Pages) MICROCHIP

258 / 402 page

PIC18FXX8

DS41159E-page 256

FIGURE 22-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

22.2

Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 22-1) keep VREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the VREF output

changes with fluctuations in that source. The absolute

accuracy of the voltage reference can be found in

Section 27.0 “Electrical Characteristics”.

22.3

Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

22.4

Effects of a Reset

A device Reset disables the voltage reference by

clearing bit CVREN (CVRCON register). This Reset

also disconnects the reference from the RA2 pin by

clearing bit CVROE (CVRCON register) and selects the

high-voltage range by clearing bit CVRR (CVRCON

are also cleared.

22.5

Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA0/AN0 pin if the

TRISA<0> bit is set and the CVROE bit (CVRCON<6>)

is set. Enabling the voltage reference output onto the

RA0/AN0 pin, with an input signal present, will increase

current consumption. Connecting RA0/AN0 as a digital

output, with CVRSS enabled, will also increase current

consumption.

The RA0/AN0 pin can be used as a simple D/A output

with limited drive capability. Due to the limited current

drive capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 22-2 shows an example buffering technique.

CVRR

CVR3

CVR0

(From CVRCON<3:0>)

16-to-1 Analog MUX

RA0/AN0/CVREF

16 Stages

CVRSS = 1

VDD VREF+

CVRSS = 1

CVRSS = 0

RA2/AN2/VREF-

CVRSS = 0

or CVREF of Comparator

CVREN

PIC18F258-E/LSQTP Datasheet(PDF) 258 Page - Microchip Technology

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