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PIC18F258-E/LSQTP Datasheet(PDF) 346 Page - Microchip Technology |
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PIC18F258-E/LSQTP Datasheet(HTML) 346 Page - Microchip Technology |
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346 / 402 page  PIC18FXX8 DS41159E-page 344 © 2006 Microchip Technology Inc. TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) FIGURE 27-7: CLKO AND I/O TIMING TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions —FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only —FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only —trc PLL Start-up Time (Lock Time) — — 2 ms — ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Param No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 ↑ to CLKO ↓ —75 200 ns (1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ —75 200 ns (1) 12 TckR CLKO Rise Time — 35 100 ns (1) 13 TckF CLKO Fall Time — 35 100 ns (1) 14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (1) 15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (1) 16 TckH2ioI Port In Hold after CLKO ↑ 0— — ns (1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) PIC18FXX8 100 — — ns 18A PIC18LFXX8 200 — — ns 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20 TIOR Port Output Rise Time PIC18FXX8 — 10 25 ns 20A PIC18LFXX8 — — 60 ns 21 TIOF Port Output Fall Time PIC18FXX8 — 10 25 ns 21A PIC18LFXX8 — — 60 ns 22† TINP INT pin High or Low Time TCY —— ns 23† TRBP RB7:RB4 Change INT High or Low Time TCY —— ns 24† TRCP RC7:RC4 Change INT High or Low Time 20 — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC. Note: Refer to Figure 27-5 for load conditions. OSC1 CLKO I/O Pin (Input) I/O Pin (Output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value |
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