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PIC18F258-E/SOSQTP Datasheet(PDF) 350 Page - Microchip Technology |
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PIC18F258-E/SOSQTP Datasheet(HTML) 350 Page - Microchip Technology |
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350 / 402 page ![]() PIC18FXX8 DS41159E-page 348 © 2006 Microchip Technology Inc. FIGURE 27-12: PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458) TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458) Note: Refer to Figure 27-5 for load conditions. RE2/CS RE0/RD RE1/WR RD7:RD0 62 63 64 65 Param No. Symbol Characteristic Min Max Units Conditions 62 TdtV2wrH Data-In Valid before WR ↑ or CS ↑ (setup time) 20 25 — — ns ns Extended Temp. range 63 TwrH2dtI WR ↑ or CS ↑ to Data-In Invalid (hold time) PIC18FXX8 20 — ns PIC18LFXX8 35 — ns 64 TrdL2dtV RD ↓ and CS ↓ to Data-Out Valid — — 80 90 ns ns Extended Temp. range 65 TrdH2dtI RD ↑ or CS ↓ to Data-Out Invalid 10 30 ns 66 TibfINH Inhibit the IBF flag bit being cleared from WR ↑ or CS ↑ —3 TCY ns |
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