ST10F273 datasheet(168/179 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F273

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24.8.18

CLKOUT and READY

VDD = 5V ± 10%, VSS = 0V, TA = -40°C to + 125°C, CL = 50pF

Table 79.

CLKOUT and READY timings

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU clock

1/2 TCL = 1 to 64 MHz

Min.

Max.

Min.

Max.

t29

CC CLKOUT cycle time

2TCL

t30

CC CLKOUT high time

–

TCL – 3.5

–

t31

CC CLKOUT low time

–

TCL – 2.5

–

t32

CC CLKOUT rise time

–

t33

CC CLKOUT fall time

–

t34

CLKOUT rising edge to

ALE falling edge

– 2 + tA

8 + tA

– 2 + tA

8 + tA

t35

Synchronous READY

setup time to CLKOUT

–

t36

Synchronous READY

hold time after CLKOUT

2–

–

t37

Asynchronous READY

low time

–

2TCL + 10

–

t58

Asynchronous READY

setup time(1)

These timings are given for characterization purposes only, in order to assure recognition at a specific

clock edge.

–

t59

Asynchronous READY

hold time (1)

2–

–

t60

Async. READY hold time

after RD, WR high

(Demultiplexed bus)(2)

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.

This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers

to the current bus cycle.

02tA + tC + tF

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