MPC8280 datasheet(314/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-6

Freescale Semiconductor

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PCI agent mode capabilities which include the ability to configure from a remote host

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Address translation units for address mapping between host and agent.

Efforts were made to keep the terminology in this chapter consistent with the PCI Specification, revision

2.2, and other PCI documentation; therefore, the terms found in Table 9-1 may differ from most

documentation for processors that implement the PowerPC architecture (for example, architecture

specification or reference manuals).

NOTE: PCI Bridge Signal Naming

PCI bridge signals are defined in most cases with the prefix “PCI_” (for

example, PCI_IRDY—see Figure 6-1). In this chapter, however, the prefix

is not used. For descriptions of PCI bridge signals, refer to Chapter 6,

“External Signals.”

9.9.1

PCI Interface Operation

The following sections discuss the operation of the PCI bus.

9.9.1.1

Bus Commands

PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on

PCI_C/BE[3-0] during the address phase of the transaction. PCI bus commands are described in Table 9-2.

Table 9-1. PCI Terminology

Term

Definition

LSB/Lower order

Represents bit 0 or the bits closest to the LSB

MSB/High order

Represents bit 31 or the bits closest to the MSB

Byte

Represents 8 bits of information

Word

Represents 16 bits or 2 bytes

Double word

Represents 32 bits or 2 words or 4 bytes

Quad word

Represents 64 bits or 2 double-words or 4 words or 8 bytes

Beat

Represents any valid data during a data transfer

Burst

Represents any 1 or more beat transfers

Edge/Clock edge

Represents the rising edge of the PCI clock

Cycle/Clock cycle

Represents the time period between clock edges

Asserted/negated

Represents the globally visible state of the signal on the clock edge

Address phase

Represents the first clock cycle where FRAME is asserted

Data phase(s)

Represents the clock cycle(s) where IRDY and TRDY are asserted

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