MPC8280 datasheet(127/1386 Pages) FREESCALE

127 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-11

2.3.1.2

MPC8280-Specific Registers

The set of registers specific to the MPC603e are also shown in Figure 2-2. Most of these are described in

the G2 Core Reference Manual and are implemented in the MPC8280 as follows:

•

MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA.

These registers facilitate the software required to search the page tables in memory.

•

IABR and IABR2. These registers facilitate the setting of instruction address breakpoints.

•

DABR and DABR2. These registers facilitate the setting of data address breakpoints.

•

IBCR and DBCR. These registers give further control to the instruction and data address

breakpoints.

The hardware implementation-dependent registers (HIDx) are implemented differently in the MPC8280,

and they are described in the following subsections.

2.3.1.2.1

Hardware Implementation-Dependent Register 0 (HID0)

Figure 2-3 shows the MPC8280 implementation of HID0.

Table 2-1 shows the bit definitions for HID0.

1112

EMCP

—

EBA

EBD

—

PAR DOZE

—

STOP

DPM

—

NHR

ICE

DCE

ILOCK DLOCK ICFI DCFI

—

IFEM

—

FBIOB

ABE

—

NOOPTI

Figure 2-3. Hardware Implementation Register 0 (HID0)

Table 2-1. HID0 Field Descriptions

Bits

Name

Description

EMCP

Enable machine check input pin

0 The assertion of the MCP does not cause a machine check exception.

1 Enables the entry into a machine check exception based on assertion of the MCP input,

detection of a cache parity error, detection of an address parity error, or detection of a data

parity error.

Note that the machine check exception is further affected by MSR[ME], which specifies whether

the processor checkstops or continues processing.

1—

Reserved

EBA

Enable/disable 60x bus address parity checking

0 Prevents address parity checking.

1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check

exception if MSR[ME] = 1.

EBA and EBD let the processor operate with memory subsystems that do not generate parity.

EBD

Enable 60x bus data parity checking

0 Parity checking is disabled.

1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception

if MSR[ME] = 1.

EBA and EBD let the processor operate with memory subsystems that do not generate parity.

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