PC312XDP512F0CAL datasheet(640/1350 Pages) FREESCALE

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Chapter 17 Memory Mapping Control (S12XMMCV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

640

Freescale Semiconductor

17.4.3

Chip Access Restrictions

17.4.3.1

Illegal XGATE Accesses

A possible access error is ﬂagged by the MMC and signalled to XGATE under the following conditions:

•

XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).

•

XGATE accesses the register space (in case of opcode or vector fetch).

•

XGATE performs a write to Flash in any modes (in case of load-store access).

•

XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode

or vector fetch accesses).

•

XGATE performs a write to non-XGATE region in RAM (RAM protection mechanism) (in case

of load-store access).

For further details refer to the XGATE Block Guide.

17.4.3.2

Illegal CPU Accesses

After programming the protection mechanism registers (see Figure 1-17, Figure 1-18, Figure 1-19, and

Figure 1-20) and setting the RWPE bit (see Figure 1-17) there are 3 regions recognized by the MMC

module:

1. XGATE RAM region

2. CPU RAM region

3. Shared Region (XGATE AND CPU)

If the RWPE bit is set the CPU write accesses into the XGATE RAM region are blocked. If the CPU tries

to write the XGATE RAM region the AVIF bit is set and an interrupt is generated if enabled. Furthermore

if the XGATE tries to write to outside of the XGATE RAM or shared regions and the RWPE bit is set, the

write access is suppressed and the access error will be ﬂagged to the XGATE module (see Section 1.4.3.1,

“Illegal XGATE Accesses” and the XGATE Block Guide).

The bottom address of the XGATE RAM region always starts at the lowest implemented RAM address.

The values stored in the boundary registers deﬁne the boundary addresses in 256 byte steps. The 256 byte

block selected by any of the registers is always included in the respective region. For example setting the

shared region lower boundary register (RAMSHL) to $C1 and the shared region upper boundary register

(RAMSHU) to $E0 deﬁnes the shared region from address $0F_C100 to address $0F_E0FF in the global

memory space (see Figure 1-25).

The interrupt requests generated by the MMC are listed in Table 1-23. Refer to the Device User Guide for

the related interrupt vector address and interrupt priority.

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