TMPR4938 datasheet(102/716 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-14

5.2.6

G-Bus Arbiter Control Register (GARBC)

0xE030

Reserved

: Type

: Initial value

Reserved

: Type

: Initial value

ARBMD

Reserved

R/W

: Type

: Initial value

Reserved

PRIORITY

R/W

: Type

000_001_010_011_100

: Initial value

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

63:32

⎯

Reserved

⎯

ARBMD

Arbitration

Mode

Specifies how to prioritize G-Bus arbitration.

0 = Fixed priority. The G-Bus arbitration priority conforms to

the content of the PRIORITY field (bits [14:0]).

1 = Round-robin (in a round-robin fashion, PCIC0 > PDMAC >

DMAC0 > DMAC1 > PCIC1)

Note: Before accessing the PCI by DMAC, specify round-robin

as the priority mode. If fixed-priority mode is selected, a

dead lock is likely to occur in PCI bus access.

R/W

30:15

⎯

Reserved

⎯

14:0

PRIORITY

Arbitration

Priority

Specifies the priority when ARBMD (bit [16]) specifies fixed-

priority mode.

[14:12] = Bus master with the highest priority

[11:9] = Bus master with the second highest priority

[8:6] = Bus master with the third highest priority

[5:3] = Bus master with the fourth highest priority

[2:0] = Bus master with the fifth highest priority

000 = PCI controller

001 = PDMAC

010 = DMAC0

011 = DMAC1

100 = PCI controller 1

A priority of PCIC > PDMAC > DMAC0 > DMAC1 > PCIC1 is

initially set up.

000_001_01

0_011_100

R/W

Figure 5.2.6 G-Bus Arbiter Control Register

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