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UPSD3422 Datasheet(PDF) 105 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 105 Page - STMicroelectronics |
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105 / 293 page  uPSD34xx Serial UART interfaces 105/293 Figure 31. UART mode 0, block diagram Figure 32. UART Mode 0, Timing Diagram 21.5 More about UART mode 1 Refer to the block diagram in Figure 33 on page 107, and timing diagram in Figure 34 on page 107. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, a '1' is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually starts at the end AI06824 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Shift Clock Serial Port Interrupt fOSC/12 REN R1 Rx Clock Start Tx Clock Start Shift Shift Send Receive T R CL DS Q 7 6 5 4 3 2 1 0 RxD P3.0 Alt Input Function RxD Pin TxD Pin AI06825 Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI Write to SCON RI Receive Shift RxD (Data In) TxD (Shift Clock) Clear RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 |
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