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UPSD3422 Datasheet(PDF) 174 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 174 Page - STMicroelectronics |
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174 / 293 page  Analog-to-digital convertor (ADC) uPSD34xx 174/293 Table 90. ADCPS register details (SFR 94h, Reset Value 00h) Table 91. ADAT0 register (SFR 95h, reset value 00h) Table 92. ADAT1 register (SFR 96h, reset value 00h) Bit Symbol Function 7:4 – Reserved 3 ADCCE ADC Conversion Reference Clock Enable 0 = ADC reference clock is disabled (default) 1 = ADC reference clock is enabled 2:0 ADCPS[2:0] ADC Reference Clock PreScaler Only three Prescaler values are allowed: ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is fOSC. ADCPS[2:0] = 1, for fOSC frequency 32MHz or less. Resulting ADC clock is fOSC/2. ADCPS[2:0] = 2, for fOSC frequency 32MHz > 40MHz. Resulting ADC clock is fOSC/4. Bit Symbol Function 7:0 – Store ADC output, Bit 7 - 0 Bit Symbol Function 7:2 – Reserved 1.. 0 – Store ADC output, Bit 9, 8 |
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